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| DS1647/DS1647P Nonvolatile Timekeeping RAM www.maxim-ic.com FEATURES Integrates NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit, and Lithium Energy Source Clock Registers Are Accessed Identically to the Static RAM. These Registers are Resident in the Eight Top RAM Locations. Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Leap Year Compensation Valid Through 2099 Power-Fail Write Protection Allows for 10% VCC Power-Supply Tolerance DS1647 Only (DIP Module): Standard JEDEC Byte-Wide 128k x 8 RAM Pinout DS1647P Only (PowerCap(R) Module Board): Surface Mountable Package for Direct Connection to PowerCap Containing Battery and Crystal Replaceable Battery (PowerCap) Power-Fail Output Pin-for-Pin Compatible with Other Densities of DS164XP Timekeeping RAM TEMP RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C PINPACKAGE 32 EDIP (0.740a) 32 EDIP (0.740a) 34 PowerCap* 34 PowerCap* PowerCap PowerCap TOP MARK** DS1647120 DS1647120 DS1647P120 DS1647P120 DS9034PC DS9034PC PIN CONFIGURATIONS TOP VIEW A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 DS1647 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 32-Pin Encapsulated DIP Package (32 Pin 740) ORDERING INFORMATION PART DS1647-120 DS1647-120+ DS1647P-120 DS1647P120+ DS9034PCX DS9034PCX+ N.C. A15 A16 PFO VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DS1647P X1 GND VBAT X2 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 A18 A17 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 34-Pin PowerCap Module Board (Uses DS9034PCX PowerCap) PowerCap is a registered trademark of Dallas Semiconductor. *DS9034PCX required (must be ordered separately). **A "+" indicates lead-free. The top mark includes a "+" symbol on lead-free devices. 1 of 11 REV: 012605 DS1647/DS1647P PIN DESCRIPTION PDIP 1 2 3 4 5 6 7 8 9 10 11 12 23 25 26 27 28 30 31 13 14 15 17 18 19 20 21 16 22 24 29 32 -- -- -- PIN PowerCap 34 3 32 30 25 24 23 22 21 20 19 18 28 29 27 26 31 33 2 16 15 14 13 12 11 10 9 17 8 7 6 5 4 1 NAME A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 A10 A11 A9 A8 A13 A17 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 GND CE OE WE VCC PFO N.C. X1, X2, VBAT FUNCTION Address Input Data Input/Output Data Input/Output Ground Active-Low Chip Enable Active-Low Output Enable Active-Low Write Enable Power-Supply Input Active-Low Power-Fail Output, Open Drain. This pin requires a pullup resistor for proper operation. No Connection Crystal Connections and Battery Connection 2 of 11 DS1647/DS1647P DESCRIPTION The DS1647 is a 512k x 8 nonvolatile static RAM with a full-function real-time clock, which are both accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any JEDEC standard 512k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and EEPROM, providing read/write nonvolatility and the addition of the real-time clock function. The realtime clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1647 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-oftolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided. PACKAGES The DS1647 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1647P after the completion of the surface mount process. Mounting the PowerCap after the surface mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX. CLOCK OPERATIONS--READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1647 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register. As long as 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was present at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that clock accuracy is not affected by the access of data. All of the DS1647 registers are updated simultaneously after the clock status is reset. Updating is within a second after the read bit is written to 0. The read bit must be a zero for a minimum of 500ms to ensure that the external registers are updated. 3 of 11 DS1647/DS1647P Figure 1. Block Diagram DS1647 Table 1. Truth Table VCC 5V 10% <4.5V >VBAT OE X X X VIL VIH X X WE X X VIL VIH VIH X X MODE Deselect Deselect Write Read Read Deselect Deselect DQ High-Z High-Z Data In Data Out High-Z High-Z High-Z POWER Standby Standby Active Active Active CMOS Standby Data-Retention Mode 4 of 11 DS1647/DS1647P SETTING THE CLOCK The MSB Bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit halts updates to the DS1647 registers. The user can then load them with the correct day, date and time data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB for the second's registers. Setting it to a 1 stops the oscillator. FREQUENCY TEST BIT Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is running, the LSB of the second's register will toggle at 512Hz. When the seconds register is being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for access remain valid (i.e., CE low, OE low, and address for seconds register remain valid and stable). CLOCK ACCURACY (DIP MODULE) The DS1647 is guaranteed to keep time accuracy to within 1 minute per month at +25C. The RTC is calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. Clock accuracy is also affected by the electrical environment and caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional information, refer to Application Note 58. CLOCK ACCURACY (POWERCAP MODULE) The DS1647 and DS9034PCX are each individually tested for accuracy. Once mounted together, the module will typically keep time accuracy to within 1.53 minutes per month (35ppm) at +25C. Clock accuracy is also affected by the electrical environment and caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional information, refer to Application Note 58. Table 2. Register Map--BANK1 ADDRESS 7FFFF 7FFFE 7FFFD 7FFFC 7FFFB 7FFFA 7FFF9 7FFF8 B7 -- X X X X X OSC W B6 -- X X FT X -- -- R B5 -- X -- X -- -- -- X DATA B4 B3 -- -- -- -- -- -- X X -- -- -- -- -- -- X X B2 -- -- -- -- -- -- -- X B1 -- -- -- -- -- -- -- X B0 -- -- -- -- -- -- -- X FUNCTION Year Month Date Day Hour Minutes Seconds Control 00-99 01-12 01-31 01-07 00-23 00-59 00-59 A R = READ BIT FT = FREQUENCY TEST OSC = STOP BIT W = WRITE BIT X = UNUSED Note: All indicated "X" bits are not dedicated to any particular function and can be used as normal RAM bits. 5 of 11 DS1647/DS1647P RETRIEVING DATA FROM RAM OR CLOCK The DS1647 is in the read mode whenever WE (write enable) is high; CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip-enable access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1647 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring high to low transition of WE and CE. The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. DATA-RETENTION MODE When VCC is within nominal limits (VCC > 4.5V) the DS1647 can be accessed as described above with read or write cycles. However, when VCC is below the power-fail point VPF (point at which write protection occurs) the internal clock registers and RAM are blocked from all access. This is accomplished internally by inhibiting access via the CE signal. At this time the power-fail output signal (PFO) will be driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the level of the internal battery supply, power input is switched from the VCC pin to the internal battery and clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal level. BATTERY LONGEVITY The DS1647 has a lithium power source that is designed to provide energy for clock activity and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1647 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25C with the internal clock oscillator running in the absence of VCC power. Each DS1647 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1647 will be longer than 10 years since no lithium battery energy is consumed when VCC is present. 6 of 11 DS1647/DS1647P ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground.....................................................-0.3V to +6.0V Operating Temperature Range (Noncondensing).....................................................0C to +70C Storage Temperature Range...........................................................................-40C to +85C Soldering Temperature (EDIP) (leads, 10 seconds)............................+260C for 10 seconds (Note 7) Soldering Temperature.......................................See IPC/JEDEC J-STD-020 Specification (Note 7) This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = 0C to +70C) PARAMETER Supply Voltage Logic 1 Voltage, All Inputs Logic 0 Voltage, All Inputs SYMBOL VCC VIH VIL MIN 4.5 2.2 -0.3 TYP 5.0 MAX 5.5 VCC + 0.3 +0.8 UNITS V V V NOTES 1 DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, TA = 0C to +70C.) PARAMETER SYMBOL Average VCC Power Supply Current ICC1 ICC2 TTL Standby Current (CE = VIH) CMOS Standby Current ICC3 (CE = VCC - 0.2V) Input Leakage Current (Any Input) IIL Output Leakage Current IOL Output Logic 1 Voltage (IOUT = -1.0mA) (DQ0-DQ7) Output Logic 0 Voltage (IOUT = +2.1mA) (DQ0-DQ7, PFO) Write-Protection Voltage VOH VOL VPF 4.0 MIN TYP 3 2 -1 -1 2.4 0.4 4.5 MAX 85 6 4.0 +1 +1 UNITS mA mA mA mA mA V V V NOTES 2, 3 2, 3 2, 3 CAPACITANCE (TA = +25C) PARAMETER Capacitance on All Pins (Except DQ) Capacitance on DQ Pins SYMBOL CI CDQ MIN TYP MAX 7 10 UNITS pF pF NOTES 7 of 11 DS1647/DS1647P AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, TA = 0C to +70C.) PARAMETER SYMBOL Read Cycle Time tRC Address Access Time tAA tCEA CE Access Time tCEZ CE Data Off Time tOEA OE Access Time tOEZ OE Data Off Time tOEL OE to DQ Low-Z tCEL CE to DQ Low-Z Output Hold from Address tOH Write Cycle Time tWC Address Setup Time tAS tCEW CE Pulse Width tAH1 Address Hold from End of Write tAH2 Write Pulse Width tWEW tWEZ WE Data Off Time tWR WE or CE Inactive Time Data Setup Time tDS tDH1 Data Hold Time High tDH2 MIN 120 TYP MAX 120 120 40 100 40 5 5 5 120 0 100 5 30 75 40 10 85 0 25 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 NOTES 5 6 8 of 11 DS1647/DS1647P READ CYCLE TIMING WRITE CYCLE TIMING 9 of 11 DS1647/DS1647P AC ELECTRICAL CHARACTERISTICS--POWER-UP/POWER-DOWN TIMING (VCC = 5.0V 10%, TA = 0C to +70C.) PARAMETER SYMBOL tPD CE or WE at VIH before Power-Down VPF (MAX) to VPF (MIN) VCC Fall Time tF VPF (MIN) to VSO VCC Fall Time tFB VSO to VPF (MIN) VCC Rise Time tRB VPF (MIN) to VPF (MAX) VCC Rise Time tR Power-Up tREC Expected Data-Retention Time +25C tDR (Oscillator On) POWER-DOWN/POWER-UP TIMING MIN 0 300 10 1 0 15 10 TYP MAX UNITS ms ms ms ms ms ms years NOTES 35 4 OUTPUT LOAD 10 of 11 DS1647/DS1647P AC TEST CONDITIONS Output Load: 50pF + 1TTL Gate Input Levels: 0 to 3V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) All voltages are referenced to ground. 2) Typical values are at +25C and nominal supplies. 3) Outputs are open. 4) Each DS1647 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined for DIP modules as a cumulative time in the absence of VCC starting from the time power is first applied by the user. 5) tAH1, tDH1 are measured from WE going high. 6) tAH2, tDH2 are measured from CE going high. 7) RTC Encapsulated DIP Modules (EDIP) can be successfully processed through conventional wavesoldering techniques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. See the PowerCap package drawing for details regarding the PowerCap package. PACKAGE INFORMATION For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. 28-pin 740 EDIP Module Document number: 56-G0002-001 32-pin PowerCap Module Document number: 56-G0003-001 11 of 11 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products * Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. |
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